page 1 of 10 20 lead 4x4 mm qfn the SP4308 is a high linearity, 5-bit rf digital step attenuator (dsa) covering 31 db attenuation range in 1db steps, and is pin compatible with the sp430x series. this 75-ohm rf dsa provides both parallel (latched or direct mode) and serial cmos control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. it also has a unique control interface that allows the user to select an initial attenuation state at power-up. the SP4308 exhibits very low insertion loss and low power consumption. this functionality is delivered in a 4x4 mm qfn footprint. the SP4308 is manufactured on sipat?s cmos process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification 75 ? rf digital attenuator 5-bit, 31 db, dc ? 4.0 ghz product description figure 1. functional schematic diagram SP4308 features ? attenuation: 1 db steps to 31 db ? flexible parallel and serial programming interfaces ? latched or direct mode ? unique power-up state selection ? positive cmos control logic ? high attenuation accuracy and linearity over temperature and frequency ? very low power consumption ? single-supply operation ? 75 ? impedance ? pin compatible with sp430x series ? packaged in a 20 lead 4x4 mm qfn table 1. electrical specifications @ +25c, v dd = 3.0 v notes: 1. device linearity will begin to degrade below 1 mhz 2. see figures on pages 4 to 6 for data across frequency. 3. note absolute maximum in table 3. 4. measured in a 50 ? system. control logic interface parallel control power-up control serial control rf input rf output switched attenuator array 5 3 2 parameter test conditions frequency minimum typical maximum units operation frequency dc 2000 mhz insertion loss 2 dc 1.2 ghz - 1.4 1.95 db attenuation accuracy any bit or bit combination dc 1.2 ghz - - (0.2 + 4% of atten setting) not to exceed +0.4 db db db 1 db compression3,4 1 mhz 1.2 ghz 30 34 - dbm input ip3 1,2,4 two-tone inputs up to +18 dbm 1 mhz 1.2 ghz - 52 - dbm return loss dc 1.2 ghz 10 13 - db switching speed 50% control to 0.5 db of final value - - 1 s figure 2. package type t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4308 page 2 of 10 table 2. pin descriptions electrostatic discharge (esd) precautions when handling this cmos device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rate specified in table 3. exposed solder pad connection the exposed solder pad on the bottom of the package must be grounded for proper device operation. notes: 1: both rf ports must be held at 0 v dc or dc blocked with an external series capacitor. 2: latch enable (le) has an internal 100 k ? resistor to v dd. 3: connect pin 12 to gnd to enable internal negative voltage generator. connect pin 12 to v ss (-v dd ) to bypass and disable internal negative voltage generator. 4. place a 10 k ? resistor in series, as close to pin as possible to avoid frequency resonance. see ?resistor on pin 1 & 3? paragraph figure 14. pin configuration (top view) latch-up avoidance unlike conventional cmos devices, cmos devices are immune to latch-up. switching frequency the pe4308 has a maximum 25 khz switching rate. resistor on pin 1 & 3 a 10 k ? resistor on the inputs to pin 1 & 3 (see figure 5) will eliminate package resonance between the rf input pin and the two digital inputs. specified attenuation error versus frequency performance is v dd pup1 pup2 v dd gnd 1 20 19 18 17 16 15 14 13 12 11 6 7 8 9 10 2 3 4 5 c16 rf1 data clock le gnd vss/gnd p/s rf2 c8 c4 c2 gnd c1 n/c 20-lead qfn 4x4mm exposed solder pad pin no. pin name description 1 c16 attenuation control bit, 16db (note 4). 2 rf1 rf port (note 1). 3 data serial interface data input (note 4). 4 clock serial interface clock input. 5 le latch enable input (note 2). 6 v dd power supply pin. 7 pup1 power-up selection bit. 8 pup2 power-up selection bit. 9 v dd power supply pin. 10 gnd ground connection. 11 gnd ground connection. 12 v ss /gnd negative supply voltage or gnd connection (note 3) 13 p/s parallel/serial mode select. 14 rf2 rf port (note 1). 15 c8 attenuation control bit, 8 db. 16 c4 attenuation control bit, 4 db. 17 c2 attenuation control bit, 2 db. 18 gnd ground connection. 19 c1 attenuation control bit, 1 db. 20 n/c no connect paddle gnd ground for proper operation table 3. absolute maximum ratings table 4. operating ranges symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c p in input power (50 ? ) +30 dbm v esd esd voltage (human body model) 500 v parameter min typ max units v dd power supply voltage 2.7 3.0 3.3 v i dd power supply current 100 a digital input high 0.7xv dd v digital input low 0.3xv dd v digital input leakage 1 a input power +24 dbm temperature range -40 85 c t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4308 page 3 of 10 evaluation kit the digital attenuator evaluation kit was designed to ease customer evaluation of the SP4308 dsa. j9 is used in conjunction with the supplied dc cable to supply v dd , gnd, and ?v dd . if use of the internal negative voltage generator is desired, then connect ?v dd (black banana plug) to ground. if an external ?v dd is desired, then apply -3 v. j1 should be connected to the lpt1 port of a pc with the supplied control cable. the evaluation software is written to operate the dsa in serial mode, so switch 7 (p/s) on the dip switch sw1 should be on with all other switches off. using the software, enable or disable each attenuation setting to the desired combined attenuation. the software automatically programs the dsa each time an attenuation state is enabled or disabled. note: jumper j6 supplies power to the evaluation board support circuits. to evaluate the power up options, first disconnect the control cable from the evaluation board. the control cable must be removed to prevent the pc port from biasing the control pins. during power up with p/s=1 high and le=1, the default power-up signal attenuation is set to the value present on the five control bits on the five parallel data inputs (c1 to c16). this allows any one of the 32 attenuation settings to be specified as the power-up state. during power up with p/s=0 high and le=0, the control bits are automatically set to one of four possible values presented through the pup interface. these four values are selected by the two power-up control bits, pup1 and pup2, as shown in the table 6. pin 20 is open and can be connected to any bias. note: resistors on pins 1 and 3 are required and should be placed as close to the part as possible to avoid package resonance and meet error specifications over frequency. figure 4. evaluation board layout figure 5. evaluation board schematic peregrine specification 102/0142 t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4308 page 4 of 10 -50 -40 -30 -20 -10 0 0 500 1000 1500 2000 output return loss (db) rf frequency (mhz) -50 -40 -30 -20 -10 0 0 500 1000 1500 2000 input return loss (db) rf frequency (mhz) 31db 16db 8db 0 5 10 15 20 25 30 35 0 500 1000 1500 2000 attenuation (db) rf frequency (mhz) 31db 16db 8db 4db 2db 1db -5 -4 -3 -2 -1 0 0 500 1000 1500 2000 insertion loss (db) rf frequency (mhz) typical performance data (25c, v dd = 3.0 v unless otherwise noted) figure 7. attenuation at major steps figure 9. output return loss at major attenuation steps (zo=75 ohms) figure 8. input return loss at major attenuation steps (zo=75 ohms) figure 6. insertion loss (zo=75 ohms) t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4308 page 5 of 10 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0 5 10 15 20 25 30 35 attenuation error (db) attenuation setting (db) 500mhz, -40c 500mhz, 85c 500mhz, 25c -2 -1.5 -1 -0.5 0 0.5 0 500 1000 1500 2000 attenuation error (db) rf frequency (mhz) 31db 16db 8db 2db -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0 5 10 15 20 25 30 35 attenuation error (db) attenuation setting (db) 1ghz, -40c 1ghz, 85c 1ghz, 25c -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0 5 10 15 20 25 30 35 attenuation error (db) attenuation setting (db) 10mhz, -40c 10mhz, 85c 10mhz, 25c figure 11. attenuation error vs. attenuation setting figure 13. attenuation error vs. attenuation setting figure 12. attenuation error vs. attenuation setting figure 10. attenuation error vs. frequency typical performance data (25c, v dd = 3.0 v unless otherwise noted) note: positive attenuation error indicates higher attenuation than target value t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4308 page 6 of 10 20 25 30 35 40 45 50 55 60 0 500 1000 1500 2000 iip3 (dbm) rf frequency (mhz) 0 5 10 15 20 25 30 35 40 0 500 1000 1500 2000 1db compression (dbm) rf frequency (mhz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0 5 10 15 20 25 30 35 attenuation error (db) attenuation setting (db) 1.2ghz, -40c 1.2ghz, 85c 1.2ghz, 25c figure 15. input 1 db compression (zo=50 ohms) figure 16. input ip3 (zo=50 ohms) figure 14. attenuation error vs. attenuation setting typical performance data (25c, v dd = 3.0 v unless otherwise noted) note: positive attenuation error indicates higher attenuation than target value t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4308 page 7 of 10 programming options parallel/serial selection either a parallel or serial interface can be used to control the SP4308. the p/s bit provides this selection, with p/s=low selecting the parallel interface and p/s=high selecting the serial interface. parallel mode interface the parallel interface consists of five cmos- compatible control lines that select the desired attenuation state, as shown in table 5. the parallel interface timing requirements are defined by figure 19 (parallel interface timing diagram), table 9 (parallel interface ac characteristics), and switching speed (table 1). for latched parallel programming the latch enable (le) should be held low while changing attenuation state control values, then pulse le high to low (per figure 19) to latch new attenuation state into device. for direct parallel programming, the latch enable (le) line should be pulled high. changing attenuation state control values will c hange device state to new attenuation. direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). table 5. truth table serial interface the pe4308?s serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. the latch is controlled by three cmos- compatible signals: data, clock, and latch enable (le). the data and clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the le input. the le input controls the latch. when le is high, the latch is transparent and the contents of the serial shift register control the attenuator. when le is brought low, data in the shift register is latched. the shift register should be loaded while le is held low to prevent the attenuator value from changing as data is entered. the le input should then be toggled high and brought low again, latching the new data. the stop bit (b0) of the data should always be low to prevent an unknown state in the device. the timing for this operation is defined by figure 17 (serial interface timing diagram) and table 8 (serial interface ac characteristics). power-up control settings the SP4308 always assumes a specifiable attenuation setting on power-up. this feature exists for both the serial and parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. when the attenuator powers up in serial mode (p/ s=1), the five control bits and a stop bit are set to whatever data is present on the five parallel data inputs (c1 to c16). this allows any one of the 32 attenuation settings to be specified as the power-up state. when the attenuator powers up in parallel mode (p/ s=0) with le=0, the control bits are automatically set to one of four possible values. these four values are selected by the two power-up control bits, pup1 and pup2, as shown in table 6 (power-up truth table, parallel mode). table 6. power-up truth table, parallel interface mode note: power up with le=1 provides normal parallel operation with c1-c16, and pup1 and pup2 are not active. p/s le pup2 pup1 attenuation state 0 0 0 0 reference loss 0 0 0 1 8 db 0 0 1 0 16 db 0 0 1 1 31 db 0 1 x x defined by c1-c16 p/s c16 c8 c4 c2 c1 attenuation state 0 0 0 0 0 0 reference loss 0 0 0 0 0 1 1 db 0 0 0 0 1 0 2 db 0 0 0 1 0 0 4 db 0 0 1 0 0 0 8 db 0 1 0 0 0 0 16 db 0 1 1 1 1 1 31 db note: not all 32 possible combinations of c1-c16 are shown. t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4308 page 8 of 10 b5 b4 b3 b2 b1 b0 c16c8c4c2c1 0 lsb (last in) msb (first in) table 7. 5-bit attenuator serial programming register map table 9. parallel interface ac characteristics figure 18. parallel interface timing diagram table 8. serial interface ac characteristics figure 17. serial interface timing diagram v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified note: the stop bit (b0) must always be low to prevent the attenuator from entering an unknown state. note: f clk is verified during the functional pattern test. serial programming sections of the functional pattern are clocked at 10 mhz to verify f clk specification. t pdsup t pdhld le t lepw parallel data c16:c1 le clock data msb lsb t lesup t sdsup t sd hl d t lepw symbol parameter min max unit f clk serial data clock frequency (note 1) 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t lesup le set-up time after last clock falling edge 10 ns t lepw le minimum pulse width 30 ns t sdsup serial data set-up time before clock rising edge 10 ns t sdhld serial data hold time after clock falling edge 10 ns symbol parameter min max unit t lepw le minimum pulse width 10 ns t pdsup data set-up time before rising edge of le 10 ns t pdhld data hold time after falling edge of le 10 ns t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4308 page 9 of 10 figure 19. package drawing 1.00 1.00 2.00 2.00 0.23 0.10 c a b exposed pad 4.00 detail a 16 15 11 5 1 6 20 10 0.50 typ 2.00 typ 0.55 2 1 detail a 0.18 0.18 0.435 0.435 seating plane 0.08 c 0.10 c 0.020 0.20 ref exposed pad & terminal pads 0.80 - c - 2.00 x 2.00 2.00 2.00 4.00 4.00 - b - - a - index area 0.25 c 1. dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. coplanarity applies to the exposed heat sink slug as well as the terminals. 3. dimensions are in millimeters. t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4308 page 10 of 10 figure 20. marking specifications figure 21. tape and reel drawing 4308 yyww zzzzz yyww = date code zzzzz = last five digits of psc lot number t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
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